Most computer systems provide a virtual address mechanism, whereby virtual addresses are mapped to physical addresses. When a request to access a memory location is made using a virtual address, the virtual address is translated into the corresponding physical address of the target memory location to which access is sought. A set of address translation tables defines the mapping between virtual addresses and physical addresses. The translation tables are normally stored in memory, so the translation of an address requires a memory access in order to read the tables. This memory access operation required to read the tables is in addition to the access operation to be performed on the target location. Thus, when virtual addressing is used, the number of memory accesses performed by a system may double relative to the number that would take place if all access requests were made by physical address. Some virtual addresses are multi-leveled in the sense that they require the mapping to be dereferenced in stages, which means that it may take two or more memory accesses to perform an address translation (thereby tripling or more the number of memory accesses that are needed to carry out one underlying access request).
In order to reduce the number of memory accesses that must take place to translate an address, many virtual address systems employ a type of cache called a translation lookaside buffer (TLB). Since memory pages that have been accessed recently are likely to be accessed again in the near future, once the address translation tables have been used to translate a virtual page descriptor into a physical page location, the correspondence between the virtual page and physical page is cached in the TLB. Every time an address translation needs to be performed, the TLB is checked to determine whether the TLB contains a cached mapping for the page on which the requested unit of memory is located. If the relevant mapping has been cached in the TLB, then the cache copy is used; otherwise, the address is translated from the translation tables. Since accessing the TLB is faster than accessing the translation tables in memory, use of a TLB speeds up performance when successive memory accesses are located on the same group of pages—which is normally the case.
TLBs create some additional issues when virtual memory is used to provide memory protection. Memory protection seeks to enforce a security policy governing which software components can perform which kinds of access (e.g. reading, writing) to which physical memory pages; this protection can be enforced by the virtual memory by controlling edits to the virtual-to-physical address translation. (This control can be exercised either by the operating system that creates the mappings or by an address translation control (ATC) system that filters changes to such mappings.) However, when an address translation is modified, old mappings may still exist in the TLB. Thus, when the address translation tables are edited to revoke some access right to a page for some software component, the component might retain access to the page until these old mappings have been flushed from the TLBs. The usual way to do this is to force any relevant TLBs to be flushed as part of such an operation.
However, flushing a TLB is expensive, particularly on shared memory multiprocessors. Every processor that might contain a stale mapping violating the new security policy has to be signaled to flush its TLB; this signaling typically requires a relatively slow interprocessor interrupt (IPI). In addition, the flush itself is relatively expensive.
In view of the foregoing, there is a need for a mechanism that overcomes the drawbacks of the prior art.